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Crusoe Processors

SEMINAR REPORT (SUBMITTED IN PARTIAL FULFILMENT OF THE AWARD OF DEGREE OF BACHELOR OF TECHNOLOGY) ON [pic] SESSION 2009-2010 UNDER THE GUIDANCE OF Mrs. Nida Haseeb (Seminar Co-ordinator) [pic] SUBMITTED BY Vikas Kumar Mishra IV YEAR INFORMATION TECHNOLOGY ROLL No. : 0600115059 INTEGRAL UNIVERSITY LUCKNOW Cellphone No. : 0522-2890812, 2890730, 3096117 Fax: 0522-2890809 Internet: www. integraluniversity. ac. in CERTIFICATE That is to certify that VIKAS KUMAR MISHRA has accomplished crucial Seminar work & ready the bonafied report on CRUSOE -PROCESSOR in passable method because the partial success for the requirement of the diploma of

B. Tech (Info Know-how) Of INTEGRAL UNIVERSITY, LUCKNOW below the steerage of his college inside his time restrict and his full effort to make his Seminar good. Mr. M. M. Tripathi Mr. Rizwan Beg (Seminar Co-ordinator) (HOD – CSE/IT) Mrs. Nida Haseeb (Seminar Co-ordinator) Miss. Nikhat Akhtar (Seminar Co-ordinator) ACKNOWLEDGEMENT I take the chance to specific my honest due to Mrs. Nida Haseeb (Division Of CSE/IT) for her invaluable recommendation and steerage for the success of this seminar.

I additionally thank Dr.

Rizwan Beg, HOD, (CSE/IT Dept). and all different workers of the division for his or her sort co-operation prolonged to me. Additionally I’m extending my gratitude to everybody who helped me within the profitable presentation of this seminar. I’m grateful to all my buddies who helped me in finishing my seminar a profitable one. I’m additionally grateful to all of the individuals who had been immediately or not directly concerned me in serving to to finish my seminar report. Vikas Kumar Mishra Roll No. :0600115059 B. Tech ( Closing Yr ) Info Know-how

INDEX |SNO. | TOPIC |PAGE NO. | | | | | |1. |Introduction | 5 | |2. |Structure |16 | |three. |Hierarchy mannequin |20 | |Four. |Instruction set |23 | |5. Efficiency |24 | |6. |Crusoe v/s Pentium die measurement |25 | |7. |Code morphing software program |26 | |Eight. |Drawbacks |27 | |9. |Conclusion |28 | |10. Refrences |29 | 1. INTRODUCTION [pic] Cell computing has been the buzzword for fairly a very long time. Cell computing gadgets like laptops, webslates & pocket book PCs have gotten widespread these days. The guts of each PC whether or not a desktop or cellular PC is the microprocessor. A number of microprocessors can be found available in the market for desktop PCs from corporations like Intel, AMD, Cyrix and many others. The cellular computing market has by no means had a microprocessor particularly designed for it.

The microprocessors utilized in cellular PCs are optimized variations of the desktop PC microprocessor. Cell computing makes very completely different calls for on processors than desktop computing, but up till now, cellular x86 platforms have merely made do with the identical previous processors initially designed for desktops. These processors eat plenty of energy, they usually get highly regarded. Once you’re on the go, a power-hungry processor means it’s important to pay a value: run out of energy earlier than you’ve completed, run extra slowly and lose software efficiency, or run via the airport with kilos of additional batteries.

A sizzling processor additionally wants followers to chill it; making the ensuing cellular laptop greater, clunkier and noisier. A newly designed microprocessor with low energy consumption will nonetheless be rejected by the market if the efficiency is poor. So any try on this regard should have a correct ‘performance-power’ stability to make sure industrial success. A newly designed microprocessor should be totally x86 appropriate that’s they need to run x86 purposes identical to typical x86 microprocessors since many of the presently obtainable software program’s have been designed to work on x86 platform.

Crusoe is the brand new microprocessor which has been designed specifically for the cellular computing market. It has been designed after contemplating the above talked about constraints. This microprocessor was developed by a small Silicon Valley startup firm known as Transmeta Corp. after 5 years of secret toil at an expenditure of $100 million. The idea of Crusoe is nicely understood from the straightforward sketch of the processor structure, known as ‘amoeba’. On this idea, the x86-architecture is an ill-defined amoeba containing options like segmentation, ASCII arithmetic, variable-length directions and many others.

The amoeba defined how a conventional microprocessor was, of their design, to be divided up into and software program. Thus Crusoe was conceptualized as a hybrid microprocessor that’s it has a software program half and a half with the software program layer surrounding the unit. The function of software program is to behave as an emulator to translate x86 binaries into native code at run time. Crusoe is a 128-bit microprocessor fabricated utilizing the CMOS course of. The chip’s design relies on a method known as VLIW to make sure design simplicity and excessive efficiency.

Moreover this it additionally makes use of Transmeta’s two patented applied sciences, particularly, Code Morphing Software program and Longrun Energy Administration. It’s a extremely built-in processor obtainable in numerous variations for various market segments. In electronics, Crusoe is a household of microprocessors from Transmeta. They use a VLIW “core”, upon which runs a software program abstraction layer, or digital machine, referred to as the Code Morphing Software program (CMS). The CMS interprets machine code directions acquired from applications operating on the chip into native directions for the core.

On this means, the chips can emulate the instruction set of different laptop architectures. Presently, that is used to permit the chips to emulate the Intel x86 instruction set. In concept, it’s potential for the CMS to be modified to deal with different instruction streams (i. e. to emulate different microprocessors). The addition of an abstraction layer between the x86 instruction stream and the implies that the structure can change with out breaking compatibility, simply by modifying the CMS. For instance Efficeon, the second-generation Crusoe, has a 256-bit-wide VLIW core versus 128-bit within the first era.

Crusoe performs in software program a number of the performance historically carried out in (e. g. instruction re-ordering), leading to less complicated with fewer transistors. The relative simplicity of the implies that Crusoe consumes much less energy (and subsequently generates much less warmth) than different x86-compatible microprocessors operating on the similar frequency. The identify is taken from the novel Robinson Crusoe. Transmeta (NASDAQ: TMTA) is an organization that develops computing applied sciences with a give attention to decreasing energy consumption in digital gadgets.

It was based in 1995 by Bob Cmelik, Dave Ditzel [1], Colin Hunter, Ed Kelly, Doug Laird, Malcolm Wing, and Greg Zyner as a US-based company that designed very lengthy instruction phrase code morphing (Microcoded) microprocessors. To this point, it has produced two x86-compatible CPU architectures: Crusoe and Efficeon. These CPUs have appeared in ultra-portable laptops, blade servers, pill PCs, a private cluster laptop, and a silent desktop, the place low energy consumption and warmth dissipation are of main significance. HistoryThroughout Transmeta’s first few years, little was identified about precisely what it could offer.

Its site went on-line in mid-1997, and for roughly two and a half years displayed nothing however the textual content “This internet web page will not be but right here. ” Info step by step got here out of the corporate, suggesting of a really lengthy instruction word-based (VLIW) design that translated x86 code into its personal native code. As Intel’s then-forthcoming “Merced” processor was additionally a VLIW design which might translate x86 code, hypothesis arose suggesting that Transmeta’s product might have supercomputer-level processing energy whereas truly being cheaper to fabricate than any providing by Intel, AMD or Cyrix.

In reality, Transmeta marketed their microprocessor know-how as terribly revolutionary and revolutionary within the low-power market phase. They’d hoped to be each energy and efficiency leaders within the x86 area. However preliminary Assessments of the Crusoe indicated the efficiency fell considerably in need of projections. [2] Additionally, throughout Crusoe growth Intel and AMD considerably ramped up speeds and started to handle rising considerations about energy consumption. So Crusoe was quickly cornered right into a low-volume, small type issue (SFF), low-power phase of the market.

In response, Transmeta rapidly re-designed its know-how, and produced the Efficeon processor. The Efficeon claimed to have twice the efficiency of the unique Crusoe CPU on the similar frequency. However the efficiency was nonetheless weak relative to the competitors, and the complexity of the chip had elevated considerably. This better measurement and energy consumption could have diluted a key market benefit Transmeta’s chips had beforehand loved over the competitors. Transmeta has employed plenty of business luminaries reminiscent of Linus Torvalds and Dave D. Taylor.

Initially, its function was saved secret, however partially as a result of it had such expertise amongst its workers, the business was consistently abuzz with rumors along with ‘conspiracy theories’ leading to glorious press relations (PR). Torvalds left Transmeta in June 2003 to dedicate himself to the additional growth of the Linux kernel. For example of know-how media hype, the corporate was as soon as named because the Most necessary firm in Silicon Valley in an Upside journal editorial. Much less nicely reported was that the corporate was by no means worthwhile whereas it was a chip vendor.

In 2002, it had a lack of $114 million , in 2003 a lack of $88 million, in 2004 a lack of $107 million. As of January 2005 the corporate introduced a strategic restructuring away from being a chip product firm to an mental property firm. That’s, as a substitute of promoting chips, it would promote know-how to be used by different chip makers. In February 2005, there was wild hypothesis that AMD would possibly purchase Transmeta. In March 2005 Transmeta introduced that it was shedding 68 folks, leaving 208 workers. About half of the remaining workers had been to work on propagating the LongRun2 energy optimization know-how inside Sony merchandise.

Sony was reported to be a key licensee of this Transmeta know-how. TimelineFounded in 1995. Company launch on January 19, 2000. [3] On November 13, 2000, Transmeta pronounces their preliminary public providing at $21/share. Inventory skyrocketed to $46/share making it the final of the good excessive tech IPOs of the bubble not surpassed by a excessive tech firm once more till Google’s IPO in 2004. In July of 2002, Transmeta expertise first set of layoffs equaling 40% of the corporate. [4] On Might 31, 2005, Transmeta introduced the signing of asset buy and license agreements with Hong Kong’s Tradition. om Know-how Restricted led by Chu Bong-Foo, the inventor of the Cangjie technique and one of many founding fathers of recent Chinese language computing. Nevertheless, because of delays in acquiring the required know-how export licenses from the US Division of Commerce, the events introduced the termination of this settlement on February 9, 2006. On August 10 2005, Transmeta introduced its first ever worthwhile quarter. On March 20 2006, GameSpot reported that Transmeta is engaged on an “unnamed” Microsoft challenge, most likely the Origami. [1]

On October 11 2006, Transmeta introduced that it had filed a lawsuit towards Intel Company for the infringement on ten of Transmeta’s US patents. The lawsuit, filed with the US District Court docket of Delaware, requested an injuction towards Intel’s persevering with gross sales of infringing merchandise and likewise requested financial compensation for damages. On February 7 2007, Transmeta closed its engineering providers departments and terminated 75 workers. The corporate introduced that it could now not develop and promote , however would give attention to the event and licensing of mental property. [5]

On July 6 2007, AMD invested $7. 5 million in Transmeta. AMD plans to make use of Transmeta’s patent portfolio associated to energy-efficient applied sciences. [6] Origins as a stealth startup The corporate started as a stealth startup. Transmeta tried to workers the corporate in secret, though hypothesis on-line was not unusual [7]. One supply of hypothesis was the corporate’s bare-bones webpage. On November 12, 1999, a cryptic remark within the HTML appeared [8]: Sure, there’s a secret message, and that is it: Transmeta’s coverage has been to stay silent about its plans till it had one thing to exhibit to the world.

On January 19th, 2000, Transmeta goes to announce and exhibit what Crusoe processors can do. Concurrently, the entire particulars will go up on this Web page for everybody on the Web to see. Crusoe will probably be cool and software program for cellular purposes. Crusoe will probably be unconventional, which is why we wished to let you realize upfront to return take a look at all the Web page in January, as a way to get the total story and have entry to the entire actual particulars as quickly as they’re obtainable. The corporate was largely profitable in hiding its ambitions till the official announcement.

Over 2000 non-disclosure agreements (NDAs) had been signed throughout the stealth interval [9]. Lawsuit towards Intel Company On October 11, 2006, Transmeta introduced that they’ve filed a lawsuit towards Intel Company for infringement of ten Transmeta U. S. patents masking laptop structure and energy effectivity applied sciences. The criticism fees that Intel has infringed and is infringing Transmeta’s patents by making and promoting a wide range of microprocessor merchandise together with at the least Intel’s Pentium III, Pentium Four, Pentium M, Core and Core 2 product line.

TechnologyThe precise Transmeta processors are in-order very lengthy instruction phrase (VLIW) cores. To execute x86 code, a pure software-based instruction translator dynamically compiles or emulates x86 code sequences, utilizing execution-hotspot guided heuristics. Whereas related applied sciences existed (WABI for Solar, FX! 32 for Alpha and IA-32 EL for Itanium) within the 1990s, the Transmeta method has set a a lot greater bar for compatibility—capable of execute all x86 directions from preliminary boot as much as the most recent multimedia directions—whereas retaining most of its core efficiency.

Transmeta claims a number of technical advantages to this method: Because the market leaders Intel and/or AMD would prolong the core x86 instruction set, Transmeta might rapidly improve their product with a software program improve slightly than requiring a respin of their . Efficiency and energy could be tuned in software program to satisfy market wants It might be comparatively easy to repair design or manufacturing flaws within the utilizing software program workarounds.

Extra time could possibly be spent concentrating on enhancing the capabilities of the core or decreasing its energy consumption with out worrying about 16 years of backward compatibility to the x86 structure. The processor might emulate a number of different architectures, presumably even on the similar time. (At its preliminary Crusoe launch, Transmeta demonstrated pico-Java and x86 operating intermixed on the native . ) Previous to Crusoe launch, rumors indicated Transmeta was counting on these advantages to develop a hybrid PowerPC and x86 processor. However Transmeta would initially focus solely on the extraordinarily low-power x86 market.

The power to rapidly replace merchandise with no respin was demonstrated in 2002 with an in-the-field improve (a obtain) to boost CPU efficiency of the Crusoe based mostly HP Compaq TC1000 pill PC. It was used once more in 2004 when NX bit and SSE3 Help had been added to the Efficeon product line with out requiring modifications. Within the discipline upgrades had been uncommon in observe because of system distributors not desirous to incur extra buyer Help prices or spend extra cash on QA for the potential upgrades or bug fixes to shipped merchandise that they had already closed the income books on.

Viability Transmeta misplaced a lot credibility and endured vital criticism as a result of poor preliminary Crusoe exhibiting with massive discrepancies between projections and actuals for each efficiency and energy. Though energy consumption was considerably higher than Intel and AMD choices, the tip consumer expertise (i. e. battery life) solely confirmed a marginal total enchancment. [2] First, the Code Morphing Software program (CMS) mixed with cache structure artificially inflated comparisons between benchmarks and real-world purposes. That is as a result of repetitive nature of benchmarks and their small footprints.

The CMS software program overhead could have truly been a key explanation for a lot decrease efficiency for a lot of real-world purposes; the straightforward VLIW core structure couldn’t compete on computationally-intensive purposes; and the southbridge interface was restricted by its low bandwidth for graphics or different I/O-intensive purposes. Some commonplace benchmarks even didn’t run, questioning the declare of full x86 compatibility. [3] The Efficeon processor addressed lots of Crusoe’s shortcomings and confirmed roughly a 2x real-world enchancment over Crusoe.

Its die was significantly smaller than Pentium Four and Pentium M, when put next in the identical course of know-how. Efficeon’s die fabricated in 90 nm is 68 mm? , which is 60% of the Pentium Four in 90 nm, at 112 mm? , with each processors possessing a 1 MB L2 cache. The notion of promoting a product into a particular thermal envelope was usually not understood by the mass of reviewers, who tended to check Efficeon to the gamut of x86 microprocessors, no matter energy consumption or software. One such instance of this criticism suggests the efficiency nonetheless considerably lagged Intel’s Pentium M (Banias) and AMD’s Cell Athlon XP. Four] For the 7 to 12 Watt thermal envelope wherein Efficeon was designed to compete, there are unsubstantiated claims that its frequency far exceeded anything available in the market, at 1. 5 GHz and seven W, whereas the Centrino on the time might solely function inside the 7 W envelope when its frequency was decreased to 1. 1 GHz. This declare additionally admittedly considers solely CPU frequency and ignores different vital components in total efficiency, reminiscent of core cycles per instruction (CPI), or reminiscence efficiency and bandwidth, which have various affect on completely different benchmarks and system configurations.

Sadly for Transmeta, different elements inside a laptop computer laptop additionally eat energy, such because the LCD show and arduous disk drive. Since laptops with Transmeta CPUs share these elements with common laptops, the web improve in battery life was not massive sufficient to make a lot distinction to prospects. TriviaOn the present 24, the fictional character Tony Almeida is listed as a former methods validation analyst at Transmeta. Very Lengthy Instruction Phrase or VLIW refers to a CPU structure designed to make the most of instruction stage parallelism (ILP). A processor that executes each instruction one after the opposite (i. . a non-pipelined scalar structure) could use processor assets inefficiently, doubtlessly resulting in poor efficiency. The efficiency could be improved by executing completely different sub-steps of sequential directions concurrently (that is pipelining), and even executing a number of directions totally concurrently as in superscalar architectures. Additional enchancment could be achieved by executing directions in an order completely different from the order they seem in this system; that is known as out-of-order execution. These three strategies all come at a price: elevated complexity.

Earlier than executing any operations in parallel, the processor should confirm that the directions do not need interdependencies. There are lots of kinds of interdependencies, however a easy instance can be a program wherein the primary instruction’s result’s used as an enter for the second instruction. They clearly can not execute on the similar time, and the second instruction can’t be executed earlier than the primary. Fashionable out-of-order processors use vital assets to be able to make the most of these strategies, because the scheduling of directions should be decided dynamically as a program executes based mostly on dependencies.

The VLIW method, however, executes operation in parallel based mostly on a set schedule decided when applications are compiled. Since figuring out the order of execution of operations (together with which operations can execute concurrently) is dealt with by the compiler, the processor doesn’t want the scheduling that the three strategies described above require. In consequence, VLIW CPUs provide vital computational energy with much less complexity (however better compiler complexity) than is related to most superscalar CPUs.

The Efficeon processor is Transmeta’s second-generation 256-bit VLIW design which employs a software program engine to transform code written for x86 processors to the native instruction set of the chip (Code Morphing Software program, aka CMS). Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW structure), Efficeon stresses computational effectivity, low energy consumption, and a low thermal footprint. Efficeon most intently mirrors the function set of Intel Pentium Four processors, though, like AMD Opteron processors, it helps a totally built-in reminiscence controller, a HyperTransport IO bus, and the NX bit, or no-execute x86 extension to PAE mode.

NX bit Help is accessible beginning with CMS model 6. zero. Four. Efficeon’s computational efficiency relative to cellular CPUs just like the Intel Pentium M is considered decrease, though little seems to be printed in regards to the relative efficiency of those competing processors. Efficeon is available in two package deal varieties: a 783 and a 592 ball grid array. Its energy consumption is reasonable (with some consuming as little as three watts at 1 GHz and seven watts at 1. 5 GHz), so it may be passively cooled. Two generations of this chip had been produced. The primary era (TM8600) was manufactured utilizing a TSMC zero. 13 micrometre course of and productized at speeds as much as 1. GHz. The second era (TM8800 and TM8820) was manufactured utilizing a Fujitsu 90 nm course of and productized at speeds starting from 1 GHz to 1. 7 GHz). Internally, the Efficeon has 2 arithmetic logic models, 2 load/retailer/add models, 2 execute models, 2 floating-point/MMX/SSE/SSE2 models, one department prediction unit, one alias unit, and one management unit. This VLIW Processor can execute a 256-VLIW phrase per cycle, which is named a molecule and subsequently has room and functionality to execute Eight 32-bit instructions (known as atoms) per cycle. The Efficeon has 128 ok instruction + 64 ok information stage 1 cache and a 1Mb stage 2 cache on the chip.

Moreover the Efficeon CMS (code morphing software program) reserves a small portion of most important reminiscence (usually 32Mb) for its translation cache of dynamically translated x86 directions. • Compact 474-pin ceramic BGA package deal is totally pin-compatible with current TM5400 and TM5600 fashions. The Transmeta Crusoe processor is an ultra-low energy, high-speed microprocessor based mostly on a sophisticated VLIW core structure. When used together with Transmeta’s x86 Code Morphing software program, the Crusoe processor supplies x86-compatible software program execution utilizing dynamic binary code translation, with out requiring code recompilation.

Along with the VLIW core, the processor incorporates separate 64Okay-byte instruction and information caches, a big 512Okay-byte L2 write-back cache, 64-bit DDR SDRAM reminiscence controller, 64-bit SDR SDRAM reminiscence controller, and 32-bit PCI controller. These extra purposeful models, that are usually a part of the core system logic that surrounds the microprocessor, permit the Crusoe processor to offer a extremely built-in and value efficient platform answer for the x86 cellular. market. The processor core operates from a zero. 9-1. V provide, leading to extraordinarily low energy consumption, even at excessive working frequencies. With energy consumption throughout typical operation as little as 150 milliwatts. 2. ARCHITECTURE [pic] The Crusoe processor incorporates integer and floating level execution models, separate instruction and information caches, a level-2 write-back cache, reminiscence administration unit, and multimedia directions. Along with these conventional processor options, the machine integrates a DDR SDRAM reminiscence controller, SDR SDRAM reminiscence controller, PCI bus controller and serial ROM interface controller.

These extra models are often a part of the core system logic that surrounds the microprocessor. The VLIW processor, together with Code Morphing software program and the extra system core logic models, permit the Crusoe processor to offer a extremely built-in, ultra-low energy, excessive efficiency platform answer for the x86 cellular market. The Crusoe processor block diagram is proven in Determine 1. FIGURE 1 Crusoe Processor Block Diagram – Mannequin TM5800 CPU Core Integer unit Floating level unit MMU L1 Instruction Cache L1 Information Cache 4K Eight-way set associative 64Okay 16-way set associative Unified TLB 256 entries Four-way set associative DDR SDRAM Controller SDR SDRAM Controller PCI Controller & Southbridge Interface DMA Multimedia Directions 64 64 Serial ROM Interface L2 WB Cache 512Okay Four-way set associative Bus Interface Mannequin TM5800 Product Temporary Crusoe Processor 7/5/2001 three of Eight 2. zero Processor Core The Crusoe processor core structure is comparatively easy by typical requirements. It’s based mostly on a Very Lengthy Instruction Phrase (VLIW) 128-bit instruction set.

Inside this VLIW structure, the management logic of the processor is saved quite simple and software program is used to manage the scheduling of directions. This enables a simplified and really easy implementation with an in-order 7-stage integer pipeline and a 10-stage floating level pipeline. By streamlining the processor and decreasing the management logic transistor rely, the performance-to-power consumption ratio could be drastically improved over conventional x86 architectures.

The Crusoe processor features a 64Okay-byte Eight-way set-associative Degree 1 (L1) instruction cache, and a 64Okay-byte 16-way set associative L1 information cache. The TM5800 mannequin additionally consists of an built-in 512Okay-byte Degree 2 (L2) write-back cache for improved efficient reminiscence bandwidth and enhanced efficiency. This cache structure assures most inner reminiscence bandwidth for efficiency intensive cellular purposes, whereas sustaining the identical low-power implementation that gives a superior performance-to-power consumption ratio relative to earlier x86 implementations.

Apart from having execution for logical, arithmetic, shift, and floating level directions, as in typical processors, the Crusoe processor has very distinctive options from conventional x86 designs. To ease the interpretation course of from x86 to the core VLIW instruction set, the generates the identical situation codes as typical x86 processors and operates on the identical 80-bit floating level numbers. Additionally, the Translation Look-aside Buffer (TLB) has the identical safety bits and handle mapping as x86 processors.

The software program part of this answer is used to emulate all different options of the x86 structure. The software program that converts x86 applications into the core VLIW directions is named Code Morphing software program. The mix of Code Morphing software program and the VLIW core collectively act as an x86-compatible answer. three. HIERARCHY MODEL [pic] . Crusoe Processor Software program Hierarchy VLIW Processor Code Morphing Software program x86 Working System (Home windows ME, Home windows 2000, Linux, and many others. ) x86 BIOS x86 Purposes x86 Appropriate Crusoe Processor Resolution x86 Software program pic] Four. INSTRUCTION SET [pic] 5. PERFORMANCE [pic] 6. Crusoe vs. Pentium Die Measurement Cell PII Cell PII Cell PIII TM3120 TM5400 Course of . 25m . 25m shrink . 18m . 22m . 18m On-chip L1 Cache 32KB 32KB 32KB 96KB 128KB On-chip L2 Cache zero 256KB 256KB zero 256KB Die Measurement 130mm2 180mm2 106mm2 77mm2 73mm2 [pic] Eight. Some drawbacks: 1. Code optimization doesn’t begin till a block of code has been executed extra the a number of instances. 2. Code translation requires clock cycles which might in any other case be utilized in performing software computation. . Conclusion 1. Transmeta has construct an X-86 processor based mostly on VLIW(very lengthy instruction phrase) know-how. 2. Code Morphing provides a brand new method to the implementation of an instruction set structure. three. Crusoe provides the facility of a excessive efficiency Intel processor consuming a fraction of energy . 10. REFERENCES http://www. wikipedia. org/ http://www. google. co. in/ http://www. esnips. com/ http://www. scribd. com/ www. transmeta. com www. efficeon. org www. crusoeseries. in

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