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Posted: June 29th, 2022
Transistor & Semi Conductor Device Fundamentals
Final Exam, ECE 448- Spring 2022, UIC Name:
Page 1 of 4
Final Exam, ECE 448 Transistors – Spring 2022
University of Illinois at Chicago
10:30 am to 12:30 pm on May 03, 2022
Name: UIN:
[30 points] PROBLEM # 1
Assume a hypothetical pn junction with the doping profile shown below, derive the
expression for the depletion width and the electric field under equilibrium conditions (Note
“a” is negative)
Final Exam, ECE 448- Spring 2022, UIC Name:
Page 2 of 4
[30 points] PROBLEM # 2
In a silicon MOS capacitor with an n-type substrate and a p + polysilicon gate (Ef = Ev),
the substrate doping is uniform with Nd = 2 × 1018 cm−3. The oxide thickness is 3 nm. There
is a p + channel contact biased at -1V relative to the substrate. The voltage drop across the
oxide is Vox = −0.6 V.
(a) Determine the state of the channel region (accumulation, flat-band, depletion, strong
inversion, etc.).
(b) Determine the applied gate voltage.
(c) Sketch the charge density, electric field and energy band diagram for the system.
Final Exam, ECE 448- Spring 2022, UIC Name:
Page 3 of 4
[20 points] PROBLEM # 3
Calculate the base transit time in a npn transistor with NDE= 1019 cm-3
, NAB = 1017 cm-3
, VBE=
0.8V and a neutral basewidth W = 0.8 μm. Assume DnB= 18 cm2 s-1 and independent of position.
Final Exam, ECE 448- Spring 2022, UIC Name:
Page 4 of 4
[20 points] PROBLEM # 4
List the steps needed for fabricating an n-MOSFET device. Draw figures to illustrate your
response clearly.
—–
ECE 448 Final Exam, Spring 2022, UIC Name: Page 1 of 4
ECE 448 Transistors Final Exam – Spring 2022
Chicago’s University of Illinois
On May 3, 2022, from 10:30 a.m. to 12:30 p.m.
[30 points] Name: UIN: PROBLEM #1 Assume a hypothetical pn junction with the doping profile shown below, and calculate the depletion width and electric field under equilibrium conditions (Note: “a” is negative).
ECE 448 Final Exam, Spring 2022, UIC Name: Page 2 of 4 [30 points] PROBLEM # 2 The substrate doping in a silicon MOS capacitor with an n-type substrate and a p + polysilicon gate (Ef = Ev) is uniform, with Nd = 2 1018 cm3. The thickness of the oxide is 3 nm. A p + channel contact is biased at -1V.
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