Posted: April 20th, 2022

VeRiLoG EaSy ISE project, or worst case, verilog on any other compiler

Question Assignment description

VERILOG design a pattern automotive wash, three packages 1basic, 2extra, and 3platinum, 1basic = SFsoapfoam, Cscrubbers, RIrinse 2extra = PSpresoak, C, SF, C, RI3platinum = PS, C, SF, C, RI, UUwax, C, RI, Ddryer, RSrepelshield, SHtireshineDesign pack by calling substate choices, for instance  1basic = goto state0 SF, then goto state1 C, goto state2 RI 2extra goto state4 PS, goto state1 C and so forth Begin when $$ inserted (easy sure no change) and wash pack chosen (three choice change), show bundle # by way of mealy output, after cycle achieved, show sum of final four digits of id utilizing 7763 For Instance, a group has the IDs 80-210523 and 80-213466 so this could show the decimal quantity 9), then reset to begin, displaying –, additionally add emergency reset button, assign buttons and switches as BTN3=Cash Paid BTN0 = resetsystem SW7 = Fundamental washing program.SW6 =Extracleaningprogram.SW5 = Platinum program1.Assume that just one button and change pressed at a time.2.Assume the shopper inserts the fitting sum of money on a regular basis, so solely sure no $ switch3.Use CLKsignal synchronizing clock with a frequency f = zero.5HZ.

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